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Active Systems Area Networks
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Project Overview

The focus of the ASAN project is to develop hardware and software technologies for the implementation of active system area networks (ASANs). The use of the term "active" refers to the ability of the network interfaces to perform application-specific as well as system level computations in addition to their traditional role of data transfer.

This project adopts the view that the network infrastructure should be an active computational entity capable of supporting certain classes of computations which would otherwise be performed on the host CPUs. The result is a unique network-wide programming model where computations are dynamically placed within the host CPUs or the NIs depending upon the quality of service demands and network/CPU resource availabilities. The project seeks to demonstrate that such an approach is a better match for data intensive network-based applications and that the advent of low-cost powerful embedded processors and configurable hardware makes such an approach economically viable and desirable.

The tangible project goals are:

  • the demonstration of configurable network interfaces (NIs) comprised of embedded processors coupled with field programmable gate arrays (FPGAs) to implement data-intensive streaming computations during communication
  • the use of the NIs' embedded processors to effectively handle associated meta-information and perform computationally non-intensive operations best performed "close" to the network
  • the movement of scheduling and other OoS management functionality to the NIs and the use of the FPGAs to provide practical implementations of computationally demanding QoS scheduling disciplines for real-time communication
  • the demonstration of an "extensible" software and quality management middleware layer that enables the dynamic placement of hardware (FPGA configurations) and software computations into the NIs and provides a uniform API to multiple heterogeneous network substrates. 
Our approach is an experimental one driven by existing application implementations. The near term objective is the construction of an experimental testbed with off-the-shelf NI cards, including Myrinet and I2O boards in our previous work and IXP-1200 routers used as communication co-processors in our current research. The experience with the testbed will be used in the design of a customized NI.
 

Acknowledgments

This research would not be possible without the generous support of our sponsors. We gratefully acknowledge the support of the National Science Foundation, the Department of Energy, Intel Corporation through its TE2000 and IXP architecture programs, and the Georgia Tech Research Corporation.
 

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Center for Experimental Research in Computer Systems