Dong Hyuk Woo, Joshua B. Fryman, Allan D. Knies, Hsien-Hsin S. Lee,
Chameleon: Virtualizing Idle Acceleration Cores of A Heterogeneous Multi-Core Processor for Caching and Prefetching
Although a large area of heterogeneous multi-core processors are occupied by parallel cores, they sit idle when running legacy sequential codes or the sequential parts of parallel applications. To address this under-utilization issue, we propose Chameleon architecture, which can dynamically virtualize the idle cores into a last-level cache, a data prefetcher, a hybrid between these two techniques, or an adaptive mode among them. We found that adaptive Chameleon improves the performance of SPECint06 and SPECfp06 by 33% and 22% on average. For the memory-intensive application category, it improves the performance by 53% and 33%.